The invention provides valuable improvements over existing ATPG (Automated Test Pattern Generation) test methodologies, on-chip scan control hardware and ATE equipment in connection with testing of digital semiconductor devices or integrated circuits (ICs). Existing ATPG test methodologies are widely used in the semiconductor industry for digital IC testing during manufacturing such that defective semiconductor devices can be identified and discarded during production test. The existing ATPG test methodologies can also be used for diagnostic purposes to identify a particular portion of digital logic/gates that often fails such that the error-prone digital logic portion may be redesigned if the yield figures are unacceptable. Existing ATPG test methodologies require the use of numerous externally accessible pins or pads of the semiconductor device to be tested. These external pins are used during production test of the semiconductor device to apply digital test patterns to the digital logic to be tested through on-chip scan-chain logic. The scan chain logic is coupled to inputs and outputs of the digital logic block of the semiconductor device or circuit. External scan pads or pins are also required for read-out of digital response patterns to the applied digital test pattern(s) and to control of an operational mode of the semiconductor device, i.e. scan mode active or normal mode operation. Furthermore, since numerous separate scan-chains coupled to different logic blocks of the digital logic are utilized for typical digital semiconductor circuits, the number of external pins that must be allocated for ATPG testing becomes large. The latter fact mandates that each of the external pins allocated for ATPG testing purposes have multiple functions such that these pins can function as ordinary data I/O pins or pads during the normal operation mode (i.e. not in scan-mode) of the semiconductor device.
Hence, the large number of external pins mandates the use of ATE equipment for ATPG testing that can physically access (through a customized probe tool) and electrically control logic states of all external/package pins of the semiconductor device. This feature limits the application of ATPG test methodologies to production test at the wafer level before the semiconductor device is packaged and shipped to the customer. Once the semiconductor device is mounted on the customer's printed circuit board (PCB), the external pins which possess ATPG functionality become electrically coupled to surrounding board circuitry which eliminates the possibility of controlling logic states and voltages on the external ATPG pins.
After the semiconductor device is attached to the customer's circuit board the board is normally tested at the customer's manufacturing facility. Hence if the semiconductor device fails, or is suspected to be failing, during board level testing the semiconductor device must be removed from the customer's board when failure analysis is required. This is a time-consuming and error-prone operation due to the number of pins, small pin pitch and miniscule dimensions of contemporary semiconductor circuits. The failed semiconductor circuit may consequently be damaged by the PCB removal operation itself. This can often make it impossible to properly diagnose or analyze the suspected or failed semiconductor device. Unfortunately, the detection of failures during the initial board level testing is important in virtually all types of applications despite the prior ATPG based production level testing being applied to semiconductor device as explained above. This is due to the desire to eliminate ‘early life failures’ of the semiconductor device which errors occur after shipment of the semiconductor device, but before the customer releases the circuit board. Furthermore, the detection of “early life failures” becomes increasingly important in safety-critical applications such as automotive, medical or aerospace.
Consequently, it would be highly beneficial to devise testing methodologies for semiconductor devices, and integral or on-chip scan chain hardware, which facilitate thorough testing and diagnosing of failing semiconductor devices while mounted in the customer's PCB. This feature allows the customer to test the failing semiconductor device at his factory premises. Furthermore, the manufacturer of the semiconductor device is capable of testing returned semiconductor devices while these remain board mounted, thereby eliminating the time-consuming and risky process of removing the device.
It would additionally be advantageous to perform the testing of the failing semiconductor device with existing digital test patterns and reuse of existing on-chip scan chain hardware developed for existing ATPG testing purposes during semiconductor manufacturing. These features will ensure high and predictable scan test coverage of the digital logic circuitry under test despite the semiconductor device being mounted in the customer's printed circuit board.
The present invention addresses the above-mentioned problems and challenges associated with existing ATPG test methodologies and on-chip scan control logic or hardware to provide the outlined desirable features and solutions together with numerous others as explained in further detail below.